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IT-CAREERNET
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From: Er. LOKESH SHARMA from IIT Roorkee. My objective is to build a career in the field of Digital/VLSI Design.
Date: Tuesday, December 27, 2005
Time: 05:44 AM
Indian Institute of Technology Roorkee Uttaranchal, India - 247667 ------------------------------------------------------------ LOKESH SHARMA M.Tech. (Electrical Engineering) IIT Roorkee, India Email : lokesh_mmec@yahoo.co.in Contact no : +91-9897888809 ---------------------------------------------------------------------------------------------------- OBJECTIVE To obtain a position in the field of VLSI/Digital Design. ---------------------------------------------------------------------------------------------------- AREAS OF INTEREST • Digital/VLSI Design and Verification • Computer Networking • Data Structures ---------------------------------------------------------------------------------------------------- EDUCATION • Currently pursuing M.Tech (Electrical Engineering) from IIT Roorkee, having CGPA* of 8.22[10] • B.Tech (Electronics & Instrumentation) from Kurukshetra University with 66.7% • 10 +2 from CBSE Board with 75.4% • 10th from CBSE Board with 77.4% *CGPA – Cumulative Grade Point Average (Scale of 10) ---------------------------------------------------------------------------------------------------- TECHNICAL SKILLS Languages : C, Verilog Hardware Description Language EDA Tools : Xilinx ISE, Active HDL Others : FPGA skills ---------------------------------------------------------------------------------------------------- ACADEMIC PROJECTS • Transit Time Flow meter Correction Unit using FPGA [M.Tech. Project] Institute/Industry: IIT Roorkee Period: July – November 2005 Brief Description The purpose of this work was to improve the accuracy of the transit time flow meter applied to closed pipes by minimizing the numerical integration error. A correction unit was designed to work for the discharge measurement which was later realized in FPGA. Results are then compared against the known flow profiles generated in MATLAB & correction unit has found to give an accuracy of ±0.5%. • Implementation of High Throughput Asynchronous FIFO in FPGA. [B.Tech. Final Year Major Project] Institue/Industry: M. M. Engineering College, Ambala affiliated to Kurukshetra University Brief Description The Asynchronous FIFO is a First-In-First-Out memory circuit which has the capability of interfacing two data processing units operating at different speeds. This memory is implemented using a circular queue structure, which permits writing and reading of data indefinitely as long as the boundary flag conditions are not met. This memory also has the capability to retransmit only bad data words, not the whole memory blocks as most standard FIFOs do. January – June 2003 • FPGA based 16-bit ALU [B.Tech. Final Year Minor Project] Institute/Industry: M. M. Engineering College, Ambala affiliated to Kurukshetra University Brief Description 16 bit Arithmetic Logic Unit (ALU) was implemented using Verilog HDL. The project can perform any 16-bit arithmetic, logic or shift operations. July – December 2002 ------------------------------------------------------------------------------------------------------ ACHIEVEMENTS • GATE Score : 99.26 percentile (All India Rank 40) in March 2004 95.36 percentile (All India Rank 220) in March 2003 • Won Chess Championship in Annual Sports meet, held at M. M. Engineering College, Ambala during 2002 – 2003. • Participated in Road Race Event (6.5 Kms), held at IIT Roorkee during September 2004. • Participated in Annual Sports Meet (5000m), held at IIT Roorkee during 2004 – 2005 . ----------------------------------------------------------------------------------------------------- PERSONAL INFORMATION Name : Lokesh Sharma Sex : Male Marital Status : Single Nationality : Indian Date of Birth : November 7, 1981 Blood Group : B+ Contact Address : G-92, Govind Bhawan, IIT Roorkee, Uttaranchal - 247667 Hobbies : Chess, Jogging Languages Known : Hindi, English Place: IIT Roorkee Lokesh Sharma M. Tech (Electrical Engineering) IIT Roorkee
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