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Professional Profiles |
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IT-CAREERNET
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From: piyush_vlsi_design_engg.
Date: Sunday, April 02, 2006
Time: 08:39 AM
Current AddressSanjay lodgeShukravar peth,hanuman chok,Tilak road,pune-1' 09822455780 Permanent AddressAmtol gate ,Atalo, Vanagar,Distt mehsana(Nor.Guj) Pin 384355.'02761-223394,09822455780E-m@il: piyush.kapadiya@gmail.com Piyush R.Kapadiya Career Objective : “Seeking challenged assignments in the field of VLSI Design and attaining a position that challenges my skill and urges me to learn and enhance my capabilities to become more competent and experienced so that I can contribute well to the growth of the concern.” Persuading Advanced Diploma In VLSI Design from UTL Technologies Ltd. Pune a concern of UTL Telecom Ltd. Professional Experience: · Presentely working in UTL Technologies Ltd ,pune as Project trainee in VLSI domain Job Profile : Digital system design using vhdl and verilog and symplify pro including Functional simulation,static timing anylysis,synthesis,various optimization Issuses and FPGA implementation. · From 11th of nov 2004 to 7th July 2005 worked as a trainee engg with compass technologies,Pune. Job Profile : Digital system design using verilog and simplify pro including functional Simulation ,static timing anylysis,synthesis,various optimization issuses . · From 15th of Mar 2004 to 8th Nov 2004 worked as a Hardware Engg. with the Karnavati infotech inc.,Ahmedabad. Job Profile : During a hardware engg servicing a motherboad,printer,keyboard,mouse, Lens-alignment on cd-rom,installation of drivers and software · From 9th of August 2003 to 27th Jan 2004 worked as a Lecturership with the Govt Poly technic ,vadnagar(Gujarat). Job Profile : During a lecturship taken subjects:Digital design,basic electronics,compuer application. Experience Summary: Experience: Two Years plus Current Employer: utl technologies ltd. Expected Salary Negotiable Willing To Relocate Yes Willing to Join: Next day Technical Skills: HDLS Vhdl/verilog Operating Systems Windows-98/2000/XP Architecture CPLD/FPGA(xcv50pq240) TOOLS Modelsim(5.4e,5.7p), Xilinx(7.1i), Leonardo Spectrum(2001b) Professional Projects: · Ethernet MAC TRANSMITTER(IEEE 802.3) : The projest includes the following functionality:· Encapsulation of the frame on receiving a start transmit signal.· Generates frame check sequence.Design is partitioned into the following blocks and modeled using VERILOG.· DEFER block· BACK OFF block· FRAME ASSEMBLER· CRC GENERATOR· TRANSMITTER I am working on Design, simulation and synthesis of DEFER,BACKOFF and TRANSMITER block using LEONARDO SPECTRUM and MODELSIM. Team Members : three Company : UTL technologies ltd.Results : currentely working. · DESIGN OF SYNCHRONOUS FIFO The project includes the design of generic synchronous fifo with the basic building blocks ,viz.,memeory array,Flag logic and expansion logic. I worked on the design of memory array ,which is built from dual ported memory cells.Thesecells allow simulataneous access between both ports of the memory,read port and write port,which gives the fifo its inherent synchronization property. Team Members : One Company : Compass Technologies (PUNE) Results : Successful completion in Six months. · MICROCONTROLLER BASED DIGITAL CLOCK Using 89c51 programmer to programme on 89c51 controller to display time,minute,second,alarm, Stopwatch on lcd display. Team Members : FourCompany : Sponsored by collegeResults : Successful completion in six months. Strength: § Very quick to learn and understand the concerned task in depth. § Innovative & Creative thinking in combination with Effective Time Management. § Good understanding of projects and Confidence to meet dead lines with apt perfection. Interest: Keen to learn any thing new-to-me related with electronics, especially related to VLSI design System. Educational Qualifications : Examination Board Institute Year Of Passing & % of marks 10th G.S.E.B B.N.Highschool,vadnagar 1997 with 77.8% 10+2(Sci.) G.H.S.E.B. Navin serve Vidhalay,vadnagar 1999 with 68.1% B.E.(Elec. & Com.) North Guj.University Sanchalchand patel college of engg. 2003with 66.6% Personal Details: Name: Kapadiya Piyush. Father's Name: Kapadiya Rajendrabhai. Languages Known: English, Hindi, Gujarati Mothers Tongue: Gujarati. Date Of Birth: 6th may 1982 Sex: Male Native Place: Vadnagar(North Gujarat) Permanent Address: Amtol gate,atalo,vadnagar,Di:mehsana(North gujarat) Nationality: Indian Marital Status: Single References: § Mr. Suhas S.Bindu , C.E.O., Compass Technologies,Pune. § Mr. Nadoda,H.O.D of Govt.Poly Technica,vadnagar. Declaration: I hereby declare that above information is true and correct to the best of my knowledge and belief. Place : Pune Date : 4 April 20046 Kapadiya Piyush R.
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