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Professional Profiles |
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IT-CAREERNET
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From: Igor Tsaritsyn is searching for positions of ASIC Engineer, Backend Engineer or Frontend Engineer
Date: Thursday, April 22, 2004
Time: 08:34 AM
Name Tsaritsyn Igor Born 15.06.61 E-mail: igor_ts@012.net.il Tel.: +972-52-2-955422 +972-9-9510841 Home address: 64, Katzenelson St., 46247, Herzliyya, Israel Present position: Senior ASIC Engineer Target Job: Senior ASIC Engineer Higher Education: 1985-88 PhD in Physics and Mathematics (Leningrad, Russia) 1978-83 MSc (Leningrad, Russia) Courses: 2000 (January-August): Hardware Designer degree (the SELA Institute for Advanced Computer Studies, Israel) The course included: Logic Design, Electronics Engineering, VHDL and C, Computer Networks, Digital Board and Embedded Systems Design etc 2000 Synopsys Workshop (Synthesis using Design Compiler) Professional employment: 2000 - present: Eastlogic Ltd, Israel (LSI Logic distributor in Israel) 3.5 years of ASIC design experience (Tel Aviv and Munich): -RTL Analysis based on VHDL and Verilog languages -Synthesis (Design Compiler) -Static Timing Analysis (Synopsys Prime Time) -Test Insertion (JTAG, NandTree, BIST and SCAN) and ATPG, using LogicVision and Mentor tools -Gate level simulation and analysis (VCS and NC-verilog simulators) -Formal verification (Synopsys Formality) -Floorplanning and Power planning using Avant! (Apollo) -Clock and Reset Tree Insertion (Avant! CTS) -Timing closure (ECO, Ramp-time fix) Computer skills: - UNIX and PC platforms - shell, tcl and scm (Apollo) scripting - Perl, VBA and C languages Languages: Fluent in English, Russian, and Hebrew Speaking German, French Particular interpersonal or communication skills: Good problem-solving, Teamwork, Communication skills Willingness to travel Recommendations: Design Center, LSI Logic Munich (Mr. Wolfgang Daub) Eastronics Ltd. Mr. Arie Eitan
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